PAM-XIAMEN provides InGaAsN epitaxially on GaAs or InP wafers as follows: Doping Remark undoped wafer substrate InGaAsN* 0.150 Al(0.3)Ga(0.7)As 0.5 undoped Al(0.3)Ga(0.7)As 0.5 ITEM Doping Thickness（wave length(um) InAs(y)P none 1.0 In(x)GaAs none 3.0 600<>600 0.25 1.0*10^18 - 0.05->0.25 1.0*10^18 - - 1.0*10^18 - S ~350
We offer the wafer structure InGaAs photodetectors as follows: Material X Thickness (nm) Dopant Doping concentration InP 1000 N (Sulfur) 3e16 In(x)GaAs 0.53 3000 U/D 5e14 InP 500 N (Sulfur) 3e16 Substrate SI (Fe) Source:PAM-XIAMEN For more information, please visit our website:http://www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
We can offer Layer structure of 703nm Laser as follows: Layer Composition Thickness (um) Doping(cm-3) Cap P+- GaAs 0.2 Zn:>1e19 Cladding p - Al0.8Ga0.2As 1 Zn:1e18 Etch stop GaInP 0.008 Zn:1e18 Top barrier Al0.45Ga0.55As 0.09 Undoped Well Al0.18Ga0.82As 0.004 Undoped Barrier Al0.45Ga0.55As 0.01 Undoped Well Al0.18Ga0.82As 0.004 Undoped Barrier Al0.45Ga0.55As 0.01 Undoped Well Al0.18Ga0.82As 0.004 Undoped Bottom barrier Al0.45Ga0.55As 0.09 Undoped Cladding n - Al0.8Ga0.2As 1.4 Si:1e18 Buffer n - GaAs 0.5 Si:1e18 Substrate n+ - GaAs S :>1e18 Source:PAM-XIAMEN For more information, please visit our website:http://www.powerwaywafer.com/, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
Highlights •Fabrication scheme for heterogenous Si-to-InP circuits on wafer level is described. •Wafer-to-wafer alignment accuracy better than 4–8 μm after bonding obtained. •Interconnects with excellent performance up to 220 GHz demonstrated. •Palladium barrier necessary when combining Al-based technology with gold based one. Abstract In order to benefit from the material properties of both InP-HBT and SiGe-BiCMOS technologies we have employed three-dimensional (3D) Benzocyclobutene (BCB)-based wafer bonding integration scheme. A monolithic wafer fabrication process based on transfer-substrate technology was developed, enabling the realization of complex hetero-integrated high-frequency circuits. Miniaturized vertical interconnects (vias) with low insertion loss and excellent broadband properties enable seamless transition between the InP and BiCMOS sub-circuits. Graphical abstract Keywords Heterojunction bipolar transistors; Indium phosphide; Monolithic integrated circuits; Three-dimensional integrated circuits; Wafer bonding; Wafer scale integration SOURCE:SCIENCEDIRECT For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com
In this paper, we demonstrated 155 nm-band multi-stacked QD-SOA grown by the strain-compensation technique on an InP(311)B substrate, and evaluated the fundamental gain characteristics and the femto-second optical pulse response, for the application to ultra-fast all-optical logic gate devices. The device length was 1650 μm, and a maximum gain of 35 dB was obtained under an injection current of 500 mA. We also input two serial femto-second duplicated pulses into the QD-SOA by changing the duration and observed the output auto-correlation waveforms. As a result, an effective carrier transition time was estimated to be about 1 ps. Keywords QD-SOA; 1550 nm-band; InP(311)B; Femto-second optical pulse response SOURCE:SCIENCEDIRECT For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com
GaN technology today is important technology player- Gallium Nitride on Silicon Carbide (GaN on SiC), Gallium Nitride on Silicon (GaN on Si) and Gallium Nitride on Sapphire (GaN on Sapphire). They are used in LED, RF and microwave devices. We can see a dilemma in the GaN supply chain compared with GaAs and its life cycle. Cost-sensitive applications will still go the path of GaAs technology. At the same time, foundries and researchers will service diverse, low-volume applications with specialty GaN processes. GaN on SiC will remain focusing on low-volume, niche applications because of higher cost of substrate material,while GaN on Si has lower efficiency though it has low cost of substrate. However we can see a bloom future due to innovation GaN technology on the road. Here would like to introduce our GaN epitaxial technology as follows: Customized GaN epitaxy on SiC,Si and Sapphire substrate for HEMTs, LEDs: No.1. C-plane (0001)GaN on 4H or 6H SiC substrate 1)Undoped GaN buffer or AlN buffer are available; 2)n-type(Si doped or undoped), p-type or semi-insulating GaN epitaxial layers available; 3)vertical conductive structures on n-type SiC; 4)AlGaN – 20-60nm thick, (20%-30%Al), Si doped buffer; 5)GaN n-type layer on 330µm+/-25um thick 2” wafer. 6) Single or double side polished, epi-ready, Ra<0.5um 7)Typical value on XRD: Wafer ID Substrate ID XRD(102) XRD(002) Thickness #2153 X-70105033 (with AlN) 298 167 679um No.2. Alx(Ga)1-xN on SiC Substrate 1) AlGaN layers, 20-30% Al; 2) Layer thickness 0.2-1 µm; 3) N type or semi-insulating SiC substrate with on-axis are available. No.3. C-plane (0001) GaN on Sapphire Substrate 1) GaN layer thickness:3-90um; 2) N type or semi-insulating GaN are available; 3) Dislocation Density: <1x10^ 8 cm-2 4) Single or double side polished, epi-ready, Ra<0.5um No.4. Alx(Ga)1-xN on Sapphire Substrate 2" GaN HEMT on Sapphire Substrate: Sapphire Nucleation Layer: AlN Buffer Layer: GaN (1800 nm) Spacer: AlN (1nm) Schottky Barrier: AlGaN (21 nm, 20%Al) Cap: GaN (1.5nm) No.5. C-plane (0001) GaN on Silicon (111) Substrate 1) GaN layer thickness:50nm-4um; 2) N type or semi-insulating GaN are available; 3) Single or double side polished, epi-ready, Ra<0.5um No.6. Alx(Ga)1-xN on Silicon (111) Substrate 1) AlGaN layers, 20-30% Al; 2)Typical undoped GaN layer: 2µm thick; 3)Sheet concentration: 1E13/cm3 No.7.Epi GaN on SiC/silicon/sapphire: Layer4. 50nm p-GaN [2.1017 cm-3] Layer3. 600nm HR-GaN [1015 cm-3]...
The design and characteristics of a low-energy ion beam deposition system are discussed. In the system, metal ions with an energy of 100 eV are deposited onto the substrate at a current density of 4–5 µA/cm2. Germanium single crystalline films are deposited on germanium (111) and silicon (111) substrate at substrate temperatures above 300°C. In the case of deposition below 200°C, films are found to be amorphous and re-crystallized by annealing above 300°C. When the ion energy over 500 eV is used, sputtering of the substrate is dominant and deposition is not observed for Ge+ ions and the silicon substrate combination. The results demonstrated the feasibility of growing thin film by low-energy ion beam deposition. soource:Iopscience For more information, please visit our website: http://www.semiconductorwafers.net, send us email at angel.ye@powerwaywafer.com or powerwaymaterial@gmail.com
We present new time integrated data on the optical emission spectra of laser produced germanium plasma using a Q-switched Nd:YAG laser (1064 nm), power density up to about 5 × 109 W cm−2 in conjunction with a set of five spectrometers covering a spectral range from 200 nm to 720 nm. Well resolved structure due to the 4p5s → 4p2 transition array of neutral germanium and a few multiplets of singly ionized germanium have been observed. Plasma temperature has been determined in the range (9000–11 000) K using four different techniques; two line ratio method, Boltzmann plot, Saha–Boltzmann plot and Marotta's technique whereas electron density has been deduced from the Stark broadened line profiles in the range (0.5–5.0) × 1017 cm−3, depending on the laser pulse energy to produce the germanium plasma. Full width at half maximum (FWHM) of a number of neutral and singly ionized germanium lines have been extracted by the Lorentzian fit to the experimentally observed line profiles. In addition, we have compared the experimentally measured relative line strengths for the 4p5s 3P0,1,2 → 4p2 3P0,1,2 multiplet with that calculated in the LS-coupling scheme revealing that the intermediate coupling scheme is more appropriate for the level designations in germanium. Source: iopscience For more information, please visit our website:http://www.semiconductorwafers.net, send us email at angel.ye@powerwaywafer.com or powerwaymaterial@gmail.com.
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