In this study, aluminium-silicon carbide (Al-SiC) metal matrix composites (MMCs) of different compositions were prepared under different compaction loads. Three different types Al-SiC composite specimens having 10%, 20% and 30% volume fractions of silicon carbide were fabricated using conventional powder metallurgy (PM) route. The specimens of different compositions were prepared under different compaction loads 10 ton and 15 ton. The effect of volume fraction of SiC particulates and compaction load on the properties of Al/SiC composites were investigated. The obtained results show that density and hardness of the composites are greatly influenced by volume fraction of silicon carbide particulates. Results also show that density, hardness and microstructure of Al-SiC composites are significantly influenced depending on the compaction load. The increase in the volume fraction of SiC enhances the density and hardness of the Al/SiC composites. For 15 ton compaction load, the composites show increased density and hardness as well as improved microstructure than the composites prepared under 10 ton compaction load. Furthermore, optical micrographs reveal that SiC particulates are uniformly distributed in the Al matrix. source:iopscience For more information, please visit our website: www.semiconductorwafers.net, send us email at angel.ye@powerwaywafer.com or powerwaymaterial@gmail.com.
It is well known that there are many arsenic precipitates in LEC GaAs, the dimensions of which are 500-2000 AA. The authors have recently found that these arsenic precipitates affect the device properties of chloride epitaxial-type MESFETS. They also affect the formation of small surface oval defects on MBE layers. To reduce the density of these arsenic precipitates, a multiple-wafer-annealing (MWA) technology has been developed in which wafers are annealed first at 1100 degrees C and then at 950 degrees C. By this annealing, highly uniform substrates with low arsenic precipitate densities, uniform PL and CL, uniform microscopic resistivity distributions and uniform surface morphology after AB etching can be obtained. These MWA wafers showed low threshold voltage variations for condensed ion-implantation-type MESFETS. In the present paper recent works are reviewed and the mechanism of arsenic precipitation is discussed from the viewpoint of stoichiometry. source:iopscience Other more CdZnTe products like CdZnTe Wafer ,CZT Crystal ,Cadmium Zinc Telluride ,welcome visit our website:www.semiconductorwafers.net Send us email at angel.ye@powerwaywafer.com or powerwaymaterial@gmail.com
The electrical properties of Au/p-CdZnTe contacts with different surface treatments, especially passivation treatment, are investigated in this paper. After the passivation, a TeO2 oxide layer with a thickness of 3.1 nm on the CdZnTe surface was identified by XPS analysis. Meanwhile, photoluminescence (PL) spectra confirmed that the passivation treatment minimized the surface trap state density and decreased the deep-level defects related to recombination of Cd vacancies. Current–voltage and capacitance–voltage characteristics were measured. It was shown that the passivation treatment could increase the barrier height of the Au/p-CdZnTe contact and decrease the leakage current. source:iopscience Other more CdZnTe products like CdZnTe Wafer ,CZT Crystal ,Cadmium Zinc Telluride ,welcome visit our website:www.semiconductorwafers.net Send us email at angel.ye@powerwaywafer.com or powerwaymaterial@gmail.com
Thermal management of high-power semiconductor lasers is of great importance since the output power and beam quality are affected by the temperature rise of the gain region. Thermal simulations of a vertical-external-cavity surface-emitting laser by a finite-element method showed that the solder layer between the semiconductor thin film consisting of the gain region and a heat sink has a strong influence on the thermal resistance and direct bonding is preferred to achieve effective heat dissipation. To realize thin-film semiconductor lasers directly bonded on a high-thermal-conductivity substrate, surface-activated bonding using an argon fast atom beam was applied to the bonding of gallium arsenide (GaAs Wafer) and silicon carbide wafer (SiC wafers). The GaAs or SiC structure was demonstrated in the wafer scale (2 in. in diameter) at room temperature. The cross-sectional transmission electron microscopy observations showed that void-free bonding interfaces were achieved. source:iopscience For more about SiC Substrate and Epitaxy or other products like SiC applications, welcome visit our website: semiconductorwafers.net Send us email at angel.ye@powerwaywafer.com or powerwaymaterial@gmail.com
We have fabricated waveguide photodiodes with high uniform characteristics on a 2-inch InP wafer introducing a novel process. The 2-inch wafer fabrication procedure was carried out successfully by utilizing SiNx deposition on the back of the wafer in order to compensate wafer warp. Almost all the measured waveguide photodiodes exhibited low darkcurrent (average 419 pA, σ= 49 pA at 10 V reverse bias voltage) throughout the 2-inch wafer, and high responsivity of 0.987 A/W (σ=0.011 A/W) was obtained in a consecutive 60-channel array at the input wavelength of 1.3 µm. In addition, uniformity of frequency response was also confirmed. source:iopscience For more information about InP wafer, GaAs wafer, Gallium Nitride Wafer etc wafer products,please visit our website: semiconductorwafers.net Send us email at angel.ye@powerwaywafer.com or powerwaymaterial@gmail.com
We have applied quinhydrone/methanol (Q/M) treatment to germanium (Ge) surfaces and shown that this treatment is also effective for passivating Ge surfaces for minority carrier lifetime measurements. Surface recombination velocity (S) of less than 20 cm/s has been obtained, which enables us to accurately evaluate the bulk lifetime of minority carriers, τb, in Ge wafer. To the best of our knowledge, this is the first report on wet chemical treatment successfully applied to Ge surfaces achieving low values of S. source:iopscience For more information , please visit our website: semiconductorwafers.net Send us email at angel.ye@powerwaywafer.com or powerwaymaterial@gmail.com
The Development of SiC and GaN Power Semiconductor Market The current state of SiC technology and market, and the development trend in the next few years. The SiC device market is promising. Sales of Schottky barrier diodes have matured and MOSFET shipments are expected to increase significantly over the next three years. According to Yole Développement analysts, SiC is very mature in terms of diodes, and GaN has no challenge at all for SiC MOSFETs with voltages of 1.2kV and above. GaN may compete with SiC MOSFETs in the 650V range, but SiC is more mature. It is expected that SiC sales will grow rapidly, and SiC will gain market share from the silicon power device market, and it is estimated that the compound growth rate will reach 28% in the next few years. IHS Markit believes that the SiC industry will continue to grow strongly, driven by growth in applications such as hybrid and electric vehicles, power electronics and photovoltaic inverters. SiC power devices mainly include power diodes and transistors (transistors, switching transistors). SiC power devices double the power, temperature,frequency, radiation immunity, efficiency and reliability of power electronics systems, resulting in significant reductions in size, weight and cost. The penetration of the SiC market is also growing, especially in China, where Schottky diodes, MOSFETs, junction-gate field effect transistors (JFETs) and other SiC discrete devices have appeared in mass-produced automotive DC-DC converters, automotive battery chargers. In some applications, GaN devices or GaN system integrated circuits may become competitors for SiC devices. The first GaN transistor to comply with the automotive AEC-Q101 specification was released by Transphorm in 2017. Moreover, GaN devices fabricated on GaN-on-Si epitaxial wafer have a relatively low cost and are easier to fabricate than any product on SiC wafers. For these reasons, GaN transistors may be the first choice for inverters in the late 2020s, and are superior to the more expensive SiC MOSFETs. GaN system integrated circuits package GaN transistors together with silicon gate driver ICs or monolithic full GaN ICs. Once their performance is optimized for mobile phones and notebook chargers and other high-volume applications, it is likely to be widely available on a wider scale. The current development of commercial GaN power diodes has not really begun because they fail to provide significant benefits relative to Si devices and are too expensive to be feasible. SiC Schottky diodes have been well used for these purposes and have a good pricing roadmap. In the manufacture field in this line, few players offer both these two materials, but Xiamen Powerway Advanced Material Co., Ltd(PAM-XIAMEN) engage in GaN and SiC materials together, its production line includes SiC substrate and epitaxy, GaN substrate, GaN HEMT epi wafer on silicon/SiC/Sapphire, and GaN based material with MQW for blue or green emission. IHS Markit expects: By 2020, th...
There is a method of controlling nucleation and lateral growth using the three-dimensional (3D) and two-dimensional (2D) growth modes to reduce the dislocation density. We performed 3D–2D-AlN growth on 6H-SiC substrates to obtain high-quality and crack-free AlN layers by low-pressure hydride vapor phase epitaxy (LP-HVPE). First, we performed 3D-AlN growth directly on a 6H-SiC substrate. With increasing V/III ratio, the AlN island density decreased and the grain size increased. Second, 3D–2D-AlN layers were grown directly on a 6H-SiC substrate. With increasing the V/III ratio of 3D-AlN, the crystalline qualities of the 3D–2D-AlN layer were improved. Third, we performed 3D–2D-AlN growth on a trench-patterned 6H-SiC substrate. The crack density was reduced to relax the stress by voids. We also evaluated the threading dislocation density by using molten KOH/NaOH etching. As a result, the estimated edge dislocation density of the 3D–2D-AlN sample was 3.9 × 108 cm−2. source:iopscience For more information , please visit our website: semiconductorwafers.net Send us email at angel.ye@powerwaywafer.com or powerwaymaterial@gmail.com
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