The fact that diffusion coefficients of most SiC dopants are negligibly small (at 1800°C) is excellent for

maintaining device junction stability, because dopants do not undesirably diffuse as the device is operated

long term at high temperatures. Unfortunately, this characteristic also largely (except for B at extreme

temperatures ) precludes the use of conventional dopant diffusion, a highly useful technique widely

employed in silicon microelectronics manufacturing, for patterned doping of SiC.

Laterally patterned doping of SiC is carried out by ion implantation. This somewhat restricts the depth

that most dopants can be conventionally implanted to <1 μm using conventional dopants and implantation

equipment. Compared to silicon processes, SiC ion implantation requires a much higher thermal budget

to achieve acceptable dopant implant electrical activation. Summaries of ion implantation processes

for various dopants can be found in . Most of these processes are based on carrying out implantation at

temperatures ranging from room temperature to 800°C using a patterned (sometimes high-temperature)

masking material. The elevated temperature during implantation promotes some lattice self-healing during

the implant, so that damage and segregation of displaced silicon and carbon atoms does not become

excessive, especially in high-dose implants often employed for ohmic contact formation. Co-implantation

of carbon with dopants has been investigated as a means to improve the electrical conductivity of the more

heavily doped implanted layers .

Following implantation, the patterning mask is stripped and a higher temperature (~1200 to 1800°C)

anneal is carried out to achieve maximum electrical activation of dopant ions. The final annealing

conditions are crucial to obtaining desired electrical properties from ion-implanted layers. At higher

implant anneal temperature, the SiC surface morphology can seriously degrade . Because sublimation

etching is driven primarily by loss of silicon from the crystal surface, annealing in silicon overpressures

can be used to reduce surface degradation during high-temperature anneals . Such overpressure can

be achieved by close-proximity solid sources such as using an enclosed SiC crucible with SiC lid and/or

SiC powder near the wafer, or by annealing in a silane-containing atmosphere. Similarly, robust deposited

capping layers such as AlN and graphite, have also proven effective at better preserving SiC surface

morphology during high-temperature ion implantation annealing .

As evidenced by a number of works, the electrical properties and defect structure of 4H-SiC doped

by ion implantation and annealing are generally inferior to SiC doped in-situ during epitaxial

growth . Naturally, the damage imposed on the SiC lattice roughly scales with implantation dose. Even

though reasonable electrical dopant activations have been achieved, thermal annealing processes

developed to date for SiC have not been able to thoroughly repair all damage imposed on the

crystal lattice by higher-dose ion implantations (such as those often used to form heavily doped layers

in preparation of ohmic contact formation, Section 5.5.3). The degraded crystal quality of highly

implanted SiC layers has been observed to degrade carrier mobilities and minority carrier lifetimes,

thereby causing significant degradation to the electrical performance of some devices . Until

large further improvements to ion-implanted doping of SiC are developed, SiC device designs will have

to account for nonideal behavior associated with SiC-implanted layers.